HY51V(S)65163HG/HGL
4M x 16Bit EDO DRAM
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extended Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read opera-
tion. The advanced circuit and process allow this device to achieve high performance and low power dissi-
pation. Features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal
or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
•
•
•
•
•
Extended data out operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
•
•
•
JEDEC standard pinout
50pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Battery back up operation(L-version)
•
Fast access time and cycle time
Part No
HY51V(S)65163HG/HGL-45
HY51V(S)65163HG/HGL-5
HY51V(S)65163HG/HGL-6
tRAC
45ns
50ns
60ns
tAA
23ns
25ns
30ns
tCAC
12ns
13ns
15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
•
Power dissipation
45ns
Active
Standby
468mW
50ns
432mW
60ns
396mW
•
Refresh cycle
Part No
HY51V65163HG*
HY51V65163HGL*
Ref
4K Ref
4K Ref
Normal
64ms
128ms
L-part
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
* : /RAS only, CBR and hidden refresh
ODERING INFORMATION
Part Number
HY51V(S)65163HG/HG(L)J-45
HY51V(S)65163HG/HG(L)J-5
HY51V(S)65163HG/HG(L)J-6
HY51V(S)65163HG/HG(L)T-45
HY51V(S)65163HG/HG(L)T-5
HY51V(S)65163HG/HG(L)T-6
(S) : Self refresh,
(L) : Low power
Access Time
45ns
50ns
60ns
45ns
50ns
60ns
Package
400mil 50pin SOJ
400mil 50pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
HYNIX [ HYNIX SEMICONDUCTOR ]
