HY57V281620A
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the
Mobile applications which require
low power consumption and extended temperature range . HY57V281620A is organized as 4banks of 2,097,152x16
H Y 5 7 V 2 8 1 6 2 0 A i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y n ch r o -
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d
b y a s i n g l e c o n t r o l c o m m a n d ( B u r s t l e n g t h o f 1 , 2 , 4 , 8 , o r f u l l p a g e ) , a n d t h e b u r s t c o u n t s e q u e n c e ( s e q u e n t i a l o r i n t e r l e a v e ) . A bu r s t o f
r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
•
All inputs and outputs referenced to positive edge of
system clock
•
•
Data mask function by UDQM or LDQM
Internal four banks operation
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HY57V281620AT-KI
HY57V281620AT-HI
HY57V281620AT-PI
HY57V281620AT-SI
HY57V281620ALT-KI
HY57V281620ALT-HI
HY57V281620ALT-PI
HY57V281620ALT-SI
Clock Frequency
133MHz
133MHz
Power
Organization
Interface
Package
Normal
100MHz
100MHz
133MHz
133MHz
Low Power
100MHz
100MHz
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4/Apr.01
HYNIX [ HYNIX SEMICONDUCTOR ]
