HY57V281620A
COMMAND TRUTH TABLE
Command
Mode Register Set
CKEn-1
H
CKEn
X
CS
L
H
No Operation
H
X
L
Bank Active
Read
H
Read with Autoprecharge
Write
H
Write with Autoprecharge
Precharge All Banks
H
Precharge selected Bank
Burst Stop
DQM
Auto Refresh
Burst-Read-Single-
WRITE
Entry
Self Refresh
1
Exit
L
H
L
H
Entry
Precharge
power down
Exit
L
H
L
H
Clock
Suspend
Entry
H
L
L
Exit
L
H
V
X
V
V
X
H
X
H
X
H
X
X
X
H
L
L
H
H
X
H
X
H
X
X
X
H
X
H
X
H
X
X
H
H
H
H
H
H
X
L
L
L
L
H
X
L
H
X
L
L
L
X
L
L
L
X
H
L
H
X
X
H
L
X
V
X
X
X
X
X
L
L
H
L
X
X
L
X
X
X
A9 Pin High
(Other Pins OP code)
MRS
Mode
RAS
L
X
H
L
CAS
L
X
H
H
WE
L
X
DQM
X
ADDR
A10/
AP
OP code
BA
Note
X
H
H
X
RA
X
H
X
L
V
L
X
L
H
L
H
X
CA
H
L
V
X
L
H
L
L
X
CA
H
H
V
X
V
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 1.3/Aug. 01
13
HYNIX [ HYNIX SEMICONDUCTOR ]
