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HY57V281620HCLT-S 参数 Datasheet PDF下载

HY57V281620HCLT-S图片预览
型号: HY57V281620HCLT-S
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行x 2米X 16位同步DRAM [4 Banks x 2M x 16bits Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 13 页 / 97 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY57V281620HC(L)T
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16
HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are syn-
chronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and
output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V281620HCT-6
HY57V281620HCT-7
HY57V281620HCT-K
HY57V281620HCT-H
HY57V281620HCT-8
HY57V281620HCT-P
HY57V281620HCT-S
HY57V281620HCLT-6
HY57V281620HCLT-7
HY57V281620HCLT-K
HY57V281620HCLT-H
HY57V281620HCLT-8
HY57V281620HCLT-P
HY57V281620HCLT-S
Clock Frequency
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.2/Aug. 01