HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
0.1
History
Defined Preliminary Specification
1)
2)
3)
4)
5)
6)
Modified FBGA Ball Configuration Typo.
Changed Functional Block Diagram from A10 to A11.
Changed V
DD
min from 3.0V to 3.135V.
Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
Insert t
AC2
Value.
Insdrt t
RAS
& CLK Value.
Remark
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Defined I
DD
Spec.
Delited Preliminary.
Changed I
DD
Spec.
133MHz Speed Added
Changed FBGA Package Size from 11x13 to 8x13.
1) Changed V
DD
min from 3.135V to 3.0V.
2) Changed V
IL
min from V
SSQ
-0.3V to -0.3V.
Modified of size erra. (Page15)
(Equation :
13.00
±
10
-> 13.00
±
0.10)
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
HYNIX [ HYNIX SEMICONDUCTOR ]
