HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Low Power Synchronous DRAM
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
State Machine
Row Active
512Kx32 BANK 3
Row
Pre
Decoder
512Kx32 BANK 2
512Kx32 BANK 1
512Kx32 BANK 0
DQ0
I/O Buffer & Logic
Sense AMP & I/O Gate
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CS
RAS
CAS
Refresh
Memory
Cell
Array
Column Active
WE
DQM0~3
Column
Pre
Decoder
DQ31
Y-Decoder
Bank Select
Column Add
Counter
A0
A1
Address Buffers
Address
Register
Burst
Counter
A10
BA1
BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line
Control
Rev. 0.3 / Sep. 2004
5