欢迎访问ic37.com |
会员登录 免费注册
发布采购

HY57V643220CLT-5 参数 Datasheet PDF下载

HY57V643220CLT-5图片预览
型号: HY57V643220CLT-5
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行X 512K X 32位同步DRAM [4 Banks x 512K x 32Bit Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 12 页 / 184 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
 浏览型号HY57V643220CLT-5的Datasheet PDF文件第2页浏览型号HY57V643220CLT-5的Datasheet PDF文件第3页浏览型号HY57V643220CLT-5的Datasheet PDF文件第4页浏览型号HY57V643220CLT-5的Datasheet PDF文件第5页浏览型号HY57V643220CLT-5的Datasheet PDF文件第6页浏览型号HY57V643220CLT-5的Datasheet PDF文件第7页浏览型号HY57V643220CLT-5的Datasheet PDF文件第8页浏览型号HY57V643220CLT-5的Datasheet PDF文件第9页  
HY57V643220C
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY57V643220C is organized as 4banks of 524,288x32.
HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
HY57V643220C(L)T-47
HY57V643220C(L)T-5
HY57V643220C(L)T-55
HY57V643220C(L)T-6
HY57V643220C(L)T-7
HY57V643220C(L)T-8
HY57V643220C(L)T-P
HY57V643220C(L)T-S
Clock Frequency
212MHz
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal/
Low Power
4Banks x
512Kbits x32
LVTTL
400mil 86pin
TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.8/Aug. 02
1