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HY57V64820HGLTP-55 参数 Datasheet PDF下载

HY57V64820HGLTP-55图片预览
型号: HY57V64820HGLTP-55
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行X 2米x 8位同步DRAM [4 Banks x 2M x 8Bit Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 11 页 / 82 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY57V64820HGTP
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-6
Parameter
Symbol
Min
CAS
Latency = 3
CAS
Latency = 2
tCK3
6
1000
tCK2
tCHW
tCLW
tAC3
10
2.5
2.5
-
-
-
5.4
10
2.5
2.5
-
-
-
5.4
Max
Min
7
1000
7.5
2.5
2.5
-
-
-
5.4
Max
Min
7.5
1000
10
2.5
2.5
-
-
5.4
Max
Min
7.5
1000
10
3
3
-
-
-
6
Max
Min
8
1000
10
3
3
-
-
6
Max
Min
10
1000
12
3
3
-
-
-
6
Max
Min
10
1000
ns
ns
ns
ns
2
CAS
Latency = 2
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
6
-
-
-
-
-
-
-
-
-
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
6
-
-
-
-
-
-
-
-
-
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
5.4
-
-
-
-
-
-
-
-
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
6
-
-
-
-
-
-
-
-
-
-
-
3
2
1
2
1
2
1
2
1
1
6
-
-
-
-
-
-
-
-
-
-
-
3
2
1
2
1
2
1
2
1
1
6
-
-
-
-
-
-
-
-
-
-
-
3
2
1
2
1
2
1
2
1
2
8
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Max
ns
-7
-K
-H
-8
-P
-S
Unit
Note
System clock
cycle time
Clock high pulse width
Clock low pulse width
CAS
Latency = 3
Access time
from clock
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in
low Z-time
CAS
Latency = 3
CLK to data
output in high
Z-time
CAS
Latency = 2
tOHZ3
5.4
tOHZ2
5.4
5.4
5.4
6
6
6
ns
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.1/ Nov. 03
7