欢迎访问ic37.com |
会员登录 免费注册
发布采购

HY57V64820HGTP-7 参数 Datasheet PDF下载

HY57V64820HGTP-7图片预览
型号: HY57V64820HGTP-7
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行X 2米x 8位同步DRAM [4 Banks x 2M x 8Bit Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 11 页 / 82 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
 浏览型号HY57V64820HGTP-7的Datasheet PDF文件第2页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第3页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第4页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第5页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第6页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第7页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第8页浏览型号HY57V64820HGTP-7的Datasheet PDF文件第9页  
HY57V64820HGTP
4 Banks x 2M x 8Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V64820HGTP-5/55/6/7
HY57V64820HGTP-K
HY57V64820HGTP-H
HY57V64820HGTP-8
HY57V64820HGTP-P
HY57V64820HGTP-S
HY57V64820HGLTP-5/55/6/7
HY57V64820HGLTP-K
HY57V64820HGLTP-H
HY57V64820HGLTP-8
HY57V64820HGLTP-P
HY57V64820HGLTP-S
Clock Frequency
200/183/166/143MHz
133MHz
133MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
100MHz
4Banks x 2Mbits x8
200/183/166/143MHz
133MHz
133MHz
Low power
125MHz
100MHz
100MHz
LVTTL
400mil 54pin TSOP II
(Pb free)
Note)
Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.1/ Nov. 03
1