HY57V651620B
AC CHARACTERISTICS I
-55
Parameter
Symbol
Min
C A S Latency = 3
C A S Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
5.4
C A S Latency = 2
tOHZ2
5.4
5.4
3
6
3
6
3
6
3
6
3
8
ns
55
1000
10
2.75
2.75
-
-
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
Max
Min
6
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
Max
Min
7
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
Max
Min
7.5
1000
10
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
Max
Min
8
1000
10
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
Max
Min
10
1000
12
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
Max
Min
10
1000
12
3
3
-
-
3
3
1
3
1
3
1
3
1
1
3
-
-
8
8
-
-
-
-
-
-
-
-
-
-
8
Max
Min
10
1000
ns
ns
ns
ns
2
C A S Latency = 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Max
ns
-6
(AC operating conditions unless otherwise noted)
-7
-75
-8
-10P
-10S
-10
Unit
Note
System clock
cycle time
Clock high pulse width
Clock low pulse width
C A S Latency = 3
Access time from
clock
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
C A S Latency = 3
CLK to data output
in high Z-time
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.9/Apr.01
7
HYNIX [ HYNIX SEMICONDUCTOR ]
