HY5DU283222Q
DESCRIPTION
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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V
DD
, V
DDQ
= 2.5V
±
5%
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 20mm x 14mm 100pin LQFP with
0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
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All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 3 and 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
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ORDERING INFORMATION
Part No.
HY5DU283222Q-4
HY5DU283222Q-45
HY5DU283222Q-5
HY5DU283222Q-55
V
DD/
V
DDQ
= 2.5V
Power Supply
Clock
Frequency
250MHz
222MHz
200MHz
183MHz
Max Data Rate
500Mbps/pin
444Mbps/pin
400Mbps/pin
366Mbps/pin
SSTL_2
20mm x 14mm
100pin LQFP
interface
Package
Rev. 1.2/Oct. 02
3
HYNIX [ HYNIX SEMICONDUCTOR ]
