HY5DU283222AF
SIMPLIFIED COMMAND TRUTH TABLE
Command
Extended Mode Register Set
Mode Register Set
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
Entry
Self Refresh
Exit
CKEn-1
H
H
H
H
H
CKEn
X
X
X
X
X
CS
L
L
H
L
L
L
RAS
L
L
X
H
L
H
CAS
L
L
X
H
H
L
WE
L
L
X
H
H
H
CA
RA
L
H
L
H
H
L
X
X
ADDR
A8/
AP
OP code
OP code
X
BA
Note
1,2
1,2
1
V
V
1
1
1,3
1
1,4
1,5
1
1
1
1
H
X
L
H
L
L
CA
V
X
V
H
H
H
H
L
X
X
H
L
H
L
L
L
L
H
L
H
L
H
L
H
L
L
H
L
L
X
H
X
H
X
H
X
V
X
H
H
L
L
X
H
X
H
X
H
X
V
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry
Precharge Power
Down Mode
Exit
H
L
X
1
1
1
1
L
H
Active Power
Down Mode
Entry
Exit
H
L
L
H
X
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.7 / Jun. 2004
7
HYNIX [ HYNIX SEMICONDUCTOR ]
