HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
FUNCTIONAL BLOCK DIAGRAM (32Mx8)
4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM
Write Data Register
2-bit Prefetch Unit
16
Bank
Control
Command
Decoder
8Mx8 / Bank0
Sense AMP
8Mx8 / Bank1
8Mx8 / Bank2
8Mx8 / Bank3
Mode
Register
Row
Decoder
16
8
Input Buffer
DQS
DM
2-bit Prefetch Unit
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
Output Buffer
8
DQ[0:7]
Column Decoder
ADD
BA
DQS
Address
Buffer
Column Address
Counter
CLK_DLL
DQS
Data Strobe
Transmitter
Data Strobe
Receiver
CLK,
/CLK
DLL
Block
Mode
Register
Rev. 0.4/ May. 02
7