HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
SIMPLIFIED COMMAND TRUTH TABLE
Command
Extended Mode Register Set
1,2
Mode Register Set
1,2
Device Deselect
1
No Operation
1
Bank Active
1
Read
1
Read with Autoprecharge
1,3
Write
1
Write with
Autoprecharge
1,4
Precharge All Banks
1,5
Precharge selected Bank
1
Read Burst Stop
1
Auto Refresh
1
Entry
Self
Refresh
1
Exit
Entry
Precharge Power
Down Mode
1
Active Power Down
Mode
1
Exit
Entry
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
CKEn
X
X
X
X
X
X
X
X
H
L
H
L
H
L
H
CS
L
L
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
RAS
L
L
X
H
L
H
H
L
H
L
L
X
H
X
H
X
H
X
V
X
CAS
L
L
X
H
H
L
L
H
H
L
L
X
H
X
H
X
H
X
V
WE
L
L
X
H
H
H
L
L
L
H
H
X
H
X
H
X
H
X
V
X
X
X
CA
CA
X
RA
L
H
L
H
H
L
X
X
ADDR
A10/
AP
OP code
OP code
X
V
V
V
X
V
BA
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No)
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or
MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be
issued after tRP period from Precharge command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no com-
mand presented to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no com-
mand presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time (tWR) is needed to
guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
*For more information about Truth Table, refer to “Device Operation” section in Hynix website.
Rev. 1.0 /Oct. 2004
9
HYNIX [ HYNIX SEMICONDUCTOR ]
