HY5FS123235AFCP
INITIALIZATION
GDDR4 SDRAMs must be powered up and initialized in a predefined manner as shown in Figure 1.
Operational procedures other than those specified may result in undefined operation.
The Mode Register and Extended Mode Registers do not have default values except EMR[A3:A2] and EMR3[A5].
If they are not programmed during the initialization sequence, it may lead to unspecified operation.
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2
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4
5
6
Apply Power to VDD
Apply power to VDDQ at same time or after power is applied to VDD
Apply VREF at same time or after power is applied to VDDQ
After power is stable, provide stable clock signals
Assert and hold RESET low
Wait a minimum of 200us
Set CKE# and A0 to the desired address & command on die termination settings,
then bring RESET High to latch in the logic state of CKE# and A0. Must be met
during this procedure. See Table 1 for the values and logic states for CKE# and A0
Bring CKE# low after t
ATH
is satisfied
Wait at least 200us referenced from the beginning of t
ATS
Issue at least 2 NOP commands
Issue a PRECHARGE ALL command followed by NOP commands until t
RP
is satisfied
Issue MRS command to the mode register and the 3 extended mode registers in
any order. t
MRD
must be met during this procedure
Issue two AUTO REFRESH commands
After t
RFC
is satisfied from the second AUTO REFRESH command and t
DL
is
satisfied, the device is ready for operation
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14
Figure 1: GDDR4 Initialization Sequence
Rev. 1.2 /June. 2008
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HYNIX [ HYNIX SEMICONDUCTOR ]
