1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD=1.8V
VDDQ=1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
HY5PS12421(L)F-X*
HY5PS12821(L)F-X*
HY5PS121621(L)F-X*
Configuration Package
128Mx4
64Mx8
32Mx16
84Ball
60Ball
Operating Frequency
Grade
-E3
-C4
-Y5
tCK(ns)
5
3.75
3
CL
3
4
5
tRCD
3
4
5
tRP
3
4
5
Unit
Clk
Clk
Clk
Note:
-X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
Rev. 1.4 / July 2006
4
HYNIX [ HYNIX SEMICONDUCTOR ]
