HY5S5B6ELFP-SE 参数 Datasheet PDF下载

256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

Document Title

4Bank x 4M x 16bits Synchronous DRAM

Revision History

Revision No.

0.1

0.2

0.3

1.0

Initial Draft

Modification of IDD Current

Modification of IDD3P & IDD3PS

IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA

Final revision

History

Draft Date

Aug. 2004

Oct. 2004

Jan. 2005

Jul. 2005

Remark

Preliminary

Preliminary

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.0 / Jul. 2005

1