HY5S7B6ALFP-6 参数 Datasheet PDF下载

512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Document Title

4Bank x 8M x 16bits Synchronous DRAM

Revision History

Revision No.

0.1

0.2

1.0

1.1

Initial Draft

Inserted 166MHz Product

Release

Insert (Page10)

DPD specification [IDD7 : 10uA min]

History

Draft Date

Aug. 2006

Sep. 2006

May. 2007

July. 2007

Remark

Preliminary

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.1 / July. 2007

1