HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
Preliminary
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3±0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (10.5mm x 8.3mm)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
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Internal four banks operation
Programmable CAS Latency ; 2, 3 Clocks
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Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
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ORDERING INFORMATION
Part No.
HY5V26CF-6
HY5V26CF-K
HY5V26CF-H
HY5V26CF-8
HY5V26CF-P
HY5V26CF-S
HY5V26C(L/S)F-6
HY5V26C(L/S)F-K
HY5V26C(L/S)F-H
HY5V26C(L/S)F-8
HY5V26C(L/S)F-P
HY5V26C(L/S)F-S
Clock Frequency
166MHz
133MHz
133MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
Low power
125MHz
100MHz
100MHz
4Banks x 2Mbits
x16
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 0.9/Jul. 02
1
HYNIX [ HYNIX SEMICONDUCTOR ]
