HY5Y2B6DLF-HE 参数 Datasheet PDF下载

HY5Y2B6DLF(P) Series

4Banks x 2M x 16bits Synchronous DRAM

Document Title

4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No.

0.1

0.2

0.3

History

Initial Draft

Changed Current Spec. of IDD1, 4 and 5

Deleted Preliminary

Draft Date

Dec. 2003

Apr. 2004

May. 2004

Remark

Preliminary

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / May. 2004

1