iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 3/23
PACKAGES
PLCC44 to JEDEC Standard
PIN CONFIGURATION PLCC44
(top view)
PIN FUNCTIONS PLCC44
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
CSN
WRN
RDN
BLFQ
CLK
INTN
RESN
D1
D3
D5
D7
GNDD
n.c.
n.c.
TEST
GNDA
IO7
VB67
IO6
IO5
VB45
IO4
Fct.
I
I
I
I
I
O
I
B
B
B
B
Description
Chip Select, active low
Write Enable, active low
Read Enable, active low
Clock Flash Mode
Clock Filter and PWM Function
Interrupt Message, active low
Reset, active low
Data Bus Bit 1
Data Bus Bit 3
Data Bus Bit 5
Data Bus Bit 7
Ground (digital section)
Test Pin
Ground (analog section)
I/O Stage 7
Power Supply Driver Stage 6+7
I/O Stage 6
I/O Stage 5
Power Supply Driver Stage 4+5
I/O Stage 4
No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
PGND
IO3
VB23
IO2
IO1
VB01
IO0
VCCA
POE
n.c.
n.c.
VCCD
D6
D4
D2
D0
A0
A1
A2
A3
A4
n.c.
Fct.
B
B
B
B
I
Description
Ground (ESD protection circuitry)
I/O Stage 3
Power Supply Driver Stage 2+3
I/O Stage 2
I/O Stage 1
Power Supply Driver Stage 0+1
I/O Stage 0
+5 V Supply Voltage (analog section)
Power Output Enable
+5 V Supply Voltage (digital section)
Data Bus Bit 6
Data Bus Bit 4
Data Bus Bit 2
Data Bus Bit 0
Address Bus Bit 0
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
B
B
B
B
B
B
B
B
B
I
I
I
I
I
Functions: I = Input, O = Output, B = bidirectional
External wiring VCCA, VCCD to +5 V and GNDA, GNDD, PGND to 0 V required.
ICHAUS [ IC-HAUS GMBH ]
