iC-MQ
PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 17/39
OPERATING MODES
iC-MQ has various modes of operation, for which the
functions of outputs PA, NA, PB, NB, PZ, NZ and ERR
are altered.
Two operating modes can be selected for the out-
put of the angle position in normal operation.
Mode
191/193
provides control signals for devices compati-
ble with 74HC191 or 74HC193, whereas in
Mode ABZ
the angle position is output incrementally as an en-
MODE(3:0)
Code
0x00
0x0F
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Operating Mode
Mode ABZ
Mode 191/193
Calibration 1
Calibration 2
Test 3*
Test 4*
Test 5*
Test 6*
Calibration 3
Lo-Signal
Hi-Signal
Test 10*
System Test*
Test 12*
—
IDDQ Test*
Hints
Addr. 0x02; bit 3:0
PA
A
CPD
TANAZ(2)
PCH1
VPAH
PS_out
PSIN
PCH1I
VTs
NA
not(A)
CPU
VREFIZ
NCH1
VPD
NS_out
NSIN
NCH1I
VTth
PB
B
CP
VREFISC
PCH2
—
PC_out
PCOS
PCH2I
—
NB
not(B)
nU/D
IBN
NCH2
CGUCK
NC_out
NCOS
NCH2I
—
PZ
Z
MR
PCH0
VDC1
IPF
PZO
PZO
VDC1
VTTFE
NZ
not(Z)
nPL
NCH0
VDC2
V05
NZO
NZO
VDC2
VTTSE
IERR
IERR
IERR
res.
ERR
ERR
ERR
ERR
IERR
coder quadrature signal with a zero pulse. Only in
these modes are the line drivers and the reverse po-
larity protection feature active.
In order to condition the input signals and to cali-
brate and test iC-MQ
Calibration
and
Test
modes are
available. Digital and analog test signals are pro-
vided; the latter must always be measured at high load
impedance.
All outputs and SCL, SDA, ERR to low level
All outputs to high level
TP
A
4
A
—
CLK6
A
8
not(A)
—
CLK1
B
4
B
—
CLK3/8
B
8
not(B)
—
Z
In
Z
In
Z
—
CLK4
TP1
not(Z)
—
ERR
ERR
—
All PU/PD resistors, oscillator and analog supply voltage deactivated.
*) Test function for iC-Haus device test only.
Table 13: Operating Modes
Mode ABZ
In
Mode ABZ
A/B signals are generated and output via
PA, NA, PB and NB. A freely configurable zero signal
is simultaneously provided at pins PZ and NZ. The dif-
ferential RS422 line drivers are active; an Nx pin con-
stantly supplies a complementary signal which is the
inversion of pin Px.
Mode 191/193
Pin
Signal
PA
NA
PB
NB
PZ
CPD
CPU
CP
nU/D
MR
Description
Clock Down Pulse
Clock Up Pulse
Clock Pulse
Count Direction (0: up, 1: down)
Asynch. Master Reset (active high)
Signal is ’1’ if index position is reached,
otherwise ’0’.
Asynch. Parallel Load Input (active low) /
Reset (active low)
Signal is ’0’ if index position is reached,
otherwise ’1’.
NZ
nPL
Mode 191/193
In
Mode 191/193
the output pins provide control sig-
nals for counter devices compatible with 74HC191 or
74HC193 according to the following table. The driving
capability (SIK) and the slew rate (SSR) of the output
drivers must be selected so that the clock pulses can
be output with a low pulse of typically 50 ns (see Elec-
trical Characteristics, 511).
Table 14: Operating mode for counter devices compat-
ible with 74HC191 or 74HC193.
Calibration 1, 2, 3
These modes are used to condition the input signals
and calibrate iC-MQ. In mode
Calibration 1
the user
can measure the IBN bias current and the zero chan-
ICHAUS [ IC-HAUS GMBH ]
