iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev D1, Page 6/29
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
Functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance)
are to be verified within the individual application using FMEA methods.
001 VDDA,
VDD
Permissible Supply Voltage
4.5
5.5
V
002 I(VDDA)
003 I(VDD)
004 Von
Supply Current in VDDA
fin() = 200 kHz; A, B, Z open
fin() = 200 kHz; A, B, Z open
15
20
mA
mA
V
Supply Current in VDD
Turn-on Threshold VDDA, VDD
Turn-on Threshold Hysteresis
3.2
200
0.3
4.4
005 Vhys
mV
V
006
Vc()hi
Clamp Voltage hi at
Vc()hi = V() - VDDA;
1.6
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF
I() = 1 mA, other pins open
007 Vc()lo
Clamp Voltage lo at
I() = -1 mA, other pins open
-1.6
0.3
-0.3
V
V
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF, NERR,
SCL, SDA, MA, SLI, SLO, A, B, Z
008
Vc()hi
Clamp Voltage hi at
NERR, SCL, SDA, MA,
SLI, SLO, A, B, Z
Vc()hi = V() - VDD;
I() = 1 mA, other pins open
1.6
Input Amplifiers and Signal Inputs PSIN, NSIN, PCOS, NCOS
101
Vos()
Input Offset Voltage
Vin() and G() in accordance with table GAIN;
G ≥ 20
-10
-15
10
15
mV
mV
G < 20
102 TCos
Input Offset Voltage
Temperature Drift
see 101
±10
µV/K
103 Iin()
104 GA
Input Current
V() = 0 V ... VDDA
-50
95
97
50
nA
%
Gain Accuracy
G() in accordance with table GAIN
G() in accordance with table GAIN
102
103
105 GArel
Gain SIN/COS Ratio Accuracy
Cut-off Frequency
%
106
fhc
G = 80
G = 2.667
150
630
kHz
kHz
107
SR
Slew Rate
G = 80
G = 2.667
2.3
8.0
V/µs
V/µs
Sine-To-Digital Conversion
201 AAabs
Absolute Angle Accuracy without referred to 360° input signal, G = 2.667,
-1.0
-0.5
-10
1.0
+0.5
10
DEG
DEG
%
calibration
Vin = 1.5 Vpp, HYS = 0
202 AAabs
Absolute Angle Accuracy after
calibration
referred to 360° input signal, HYS = 0, internal
signal amplitude of 2 ... 4 Vpp
±0.35
203
AArel
Relative Angle Accuracy
referred to signal periods at A, resp. B
(see Fig. 1);
G = 2.667, Vin = 1.5 Vpp, SELRES = 1024,
FCTR = 0x0004 ... 0x00FF, fin < finmax
(see table 15)
Reference Voltage Output VREF
801 VREF
Reference Voltage
I(VREF) = -1 mA ... +1 mA
48
52
90
%
VDDA
Oscillator
A01
fosc()max Permissible Max. Oscillator
Frequency
presented at pin SCL with subdivision
of 2048;
MHz
A02
fosc()
Oscillator Frequency
presented at pin SCL with subdivision
of 2048;
VDDA = VDD = 5 V ±10 %
VDDA = VDD = 5 V
56
60
90
85
MHz
MHz
74
A03 TCosc
A04 VCosc
Oscillator Frequency Tempera-
ture Drift
VDDA = VDD = 5 V
-0.1
%/K
Oscillator Frequency Power Sup-
ply Dependance
+9
%/V
ICHAUS [ IC-HAUS GMBH ]
