ICmic
ICM7363/7343/7323
Q
UAD
12/10/8-
BIT
V
OLTAGE
-O
UTPUT
DAC
S
IC MICROSYSTEMS
DETAILED DESCRIPTION
The ICM7363 is a 12-bit quad voltage output DAC. The
ICM7343 is the 10-bit version of this family and the
ICM7323 is the 8-bit version.
This family of DACs employs a resistor string architecture
guaranteeing monotonic behavior. There is a 1.25V
onboard reference and a wide operating supply range of
2.7V to 5.5V.
Reference Input and Output
Each DAC has its own reference input pin which can be
driven from ground to V
DD
-1.5V. The input resistance on
each of these pins is typically 41 kΩ. There is a gain of two
in the output amplifiers which means they swing from
ground at code 0 to 2 x V
REF IN
at full-scale :
Vout = 2 x (V
REF IN
xD)/2
n
Where D=digital input (decimal) and n= number of bits, i.e.
12 for ICM7363, 10 for ICM7343 and 8 for ICM7323.
There is also an onboard band-gap reference on all these
parts. This reference output is nominally 1.25V and is
brought out to a separate pin, REFOUT and can be used
to drive the reference input of the DACs. The outputs will
nominally swing from 0 to 2.5V when using this reference.
Output Amplifier
Each DAC has its own output amplifier with a wide output
voltage swing. The actual swing of the output amplifier will
be limited by offset error and gain error. See the
Applications Information Section for a more detailed
discussion.
The amplifiers are configured in a gain of 2 with internal
gain resistors of about 50 kΩ. The output swing will be
from 0V to 2 x V
REF IN
at full-scale.
The output amplifier can drive a load of 2.0 kΩ to V
DD
or
GND in parallel with a 500 pF load capacitance.
The output amplifier has a full-scale typical settling time of
8
µs
and it dissipates about 150
µA
with a 5V supply
voltage.
Serial Interface and Input Logic
This quad DAC family uses a standard 3-wire connection
compatible with SPI/QSPI interfaces. There is also a serial
data output pin that allows daisy-chaining. Data is loaded
in 16-bit words which consist of 4 address and control bits
(MSBs) followed by 12 bits of data (see table 1). The
ICM7343 has the last two LSBs as don’t cares and the
ICM7323 has the last 4 LSBs as don’t cares. Each DAC is
double buffered with an input latch and a DAC latch.
All the digital inputs are CMOS/TTL compatible. The
current dissipation of the device however, will be higher
when the inputs are driven at TTL levels.
The output of the 16-bit input shift register is available at
the SDO pin. Data is clocked in on the rising edge of SCK
which has a Schmitt trigger internally to allow for noise
immunity on the SCK pin. This specially eases the use for
opto-coupled interfaces.
The CS pin must be low when data is being clocked into
the part. After the 16
th
clock pulse the CS pin must be
pulled high (level-triggered) for the data to be transferred
to an input bank of latches. The CS pin also disables the
SCK pin internally when pulled high and the SCK pin must
be low before the CS pin is pulled back low. As the CS pin
is pulled high the shift register contents are transferred to
a bank of 16 latches. The 4 bit control word (C3~C0) is
then decoded and the appropriate DAC is updated or
loaded depending on the control word (see Table 1).
Each DAC has a double-buffered input with an input latch
and a DAC latch. The DAC output will swing to its new
value when data is loaded into the DAC latch. For each
DAC, the user has three options: loading only the input
latch, updating the DAC with data previously loaded into
the input latch or loading the input latch and updating the
DAC at the same time with a new code. The user also has
the ability to perform this operation simultaneously for all
DACs as shown in Table 1.
Power-On Reset
There is a power-on reset on board that will clear the
contents of all the latches to all 0s on power-up and the
DAC voltage outputs will go to ground. The CLR pin will
also perform this same operation asynchronously when it
is pulled low.
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
7
ICMIC [ IC MICROSYSTEMS ]
