欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24012S-3 参数 Datasheet PDF下载

X24012S-3图片预览
型号: X24012S-3
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 14 页 / 271 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X24012S-3的Datasheet PDF文件第1页浏览型号X24012S-3的Datasheet PDF文件第2页浏览型号X24012S-3的Datasheet PDF文件第4页浏览型号X24012S-3的Datasheet PDF文件第5页浏览型号X24012S-3的Datasheet PDF文件第6页浏览型号X24012S-3的Datasheet PDF文件第7页浏览型号X24012S-3的Datasheet PDF文件第8页浏览型号X24012S-3的Datasheet PDF文件第9页  
X24012  
DEVICE OPERATION  
Clock and Data Conventions  
Data states on the SDA line can change only during SCL  
LOW. SDA state changes during SCL HIGH are  
The X24012 supports a bidirectional bus oriented proto- col.  
The protocol defines any device that sends data  
reserved for indicating start and stop conditions. Refer to  
Figures 1 and 2.  
onto the bus as a transmitter, and the receiving device as  
the receiver. The device controlling the transfer is a  
master and the device being controlled is the slave. The  
master will always initiate data transfers and provide the  
Start Condition  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL is  
clock for both transmit and receive operations. Therefore, the  
X24012 will be considered a slave in all  
HIGH. The X24012 continuously monitors the SDA and SCL  
lines for the start condition and will not respond to  
any command until this condition has been met.  
applications.  
Figure 1. Data Validity  
SCL  
SDA  
DATA  
CHANGE  
DATA STABLE  
3847 FHD F05  
Figure 2. Definition of Start and Stop  
SCL  
SDA  
3847 FHD F06  
START BIT  
STOP BIT  
3