X24012
WRITE CYCLE LIMITS
Symbol
t
WR(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
3847 PGM T10
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24012
address.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
X24012
ADDRESS
3847 FHD F04
Notes:(5)
Typical values are for T
A
= 25°C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
120
RESISTANCE (KΟ)
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
OUTPUTS
Will be
steady
V
R
MIN
100
80
60
40
20
0
0
=
CC MAX
I
OL MIN
R
C
BUS
t
=1.8KΟ
R
MAX
=
MAX.
RESISTANCE
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
MIN.
RESISTANCE
20 40
60
80100120
3847 FHD F16
Allowed
N/A
BUS CAPACITANCE (pF)
11
ICMIC [ IC MICROSYSTEMS ]
