X24320
Bus Timing
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
SDA IN
t
AA
t
DH
t
BUF
SDA OUT
7035 FM 14
Write Cycle Limits
Symbol
t
WC
(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
7003 FRM T11
Notes: (5)Typical values are for T
A
= 25°C and nominal supply voltage (5V).
(6)t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle.
During the write cycle, the X24320 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does
not respond to its slave address.
Bus Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WC
STOP
CONDITION
START
CONDITION
7035 FM 15
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
RESISTANCE (KΟ)
V
R
MIN
CC MAX
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
OUTPUTS
Will be
steady
100
80
60
40
20
0
0
=
I
OL MIN
R
C
BUS
t
=1.8KΟ
R
MAX
=
Will change
from Low to
MAX.
RESISTANCE
High
May change
from High to
High
Will change
from High to
Low
MIN.
RESISTANCE
Low
Changing:
State Not
Don’t Care:
Changes
20
40
60
80 100120
7035 FM 16
Allowed
N/A
Known
Center Line
is High
BUS CAPACITANCE (pF)
Impedance
13
7035 FM 17
ICMIC [ IC MICROSYSTEMS ]
