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X24320V14IG 参数 Datasheet PDF下载

X24320V14IG图片预览
型号: X24320V14IG
PDF下载: 下载PDF文件 查看货源
内容描述: 400kHz的2线串行E2PROM与锁座 [400KHz 2-Wire Serial E2PROM with Block Lock]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 17 页 / 302 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24320  
READ OPERATIONS  
Read operations are initiated in the same manner as write  
operations with the exception that the R/W bit of  
Acknowledge Polling  
The maximum write cycle time can be significantly  
reduced using Acknowledge Polling. To initiate  
the Slave Address Byte is set to one. There are three basic  
read operations: Current Address Reads,  
Acknowledge Polling, the master issues a start condition  
followed by the Slave Address Byte for a write or  
Random Reads, and Sequential Reads.  
read operation. If the device is still busy with the  
internal write cycle, then no ACK will be returned. If the  
Current Address Read  
Internally, the device contains an address counter that  
maintains the address of the last word read or written  
device has completed the internal write operation, an ACK  
will be returned and the host can then proceed  
with the read or write operation. Refer to figure 7 .  
incremented by one. After a read operation from the last  
address in the array, the counter will “roll over” to the first  
address in the array. After a write operation to  
Figure 7. Acknowledge Polling Sequence  
the last address in a given page, the counter will “roll  
BYTE LOAD COMPLETED  
BY ISSUING STOP.  
ENTER ACK POLLING  
over” to the first address on the same page.  
Upon receipt of the Slave Address Byte with the R/W bit set  
to one, the device issues an acknowledge and  
then transmits the eight bits of the Data Byte. The  
master terminates the read operation when it does not  
ISSUE  
START  
respond with an acknowledge during the ninth clock and  
then issues a stop condition. Refer to figure 8 for the address  
acknowledge, and data transfer sequence.  
ISSUE SLAVE  
ADDRESS BYTE  
ISSUE STOP  
(READ OR WRITE)  
It should be noted that the ninth clock cycle of the read  
operation is not a “don’t care "  
.” To terminate a read  
operation, the master must either issue a stop condition  
during the ninth cycle or hold SDA HIGH during  
the ninth clock cycle and then issue a stop condition.  
ACK  
RETURNED?  
NO  
YES  
HIGH  
VOLTAGE  
Figure 8. Current Address Read Sequence  
NO  
CYCLE COMPLETE.  
CONTINUE  
SEQUENCE?  
S
T
A
R
T
SIGNALS  
FROM THE  
MASTER  
S
T
SLAVE  
ADDRESS  
O
P
YES  
SDA BUS  
S 1 01 0  
1
P
CONTINUE NORMAL  
READ OR WRITE  
COMMAND SEQUENCE  
A
C
K
ISSUE STOP  
SIGNALS  
FROM THE  
SLAVE  
DATA  
7035 FM 10  
PROCEED  
7035 FM 09  
7