X24645
Page Write
The X24645 is capable of a 32-byte page write operation.
It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to thirty-one more bytes. After the receipt of
each byte, the X24645 will respond with an acknowledge.
ISSUE
START
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
After the receipt of each byte, the five low order
address bits are internally incremented by one. The high
order eight bits of the address remain constant. If the
master should transmit more than 32 bytes prior to gen-
erating the stop condition, the address counter will “roll
over” and the previously written data will be overwritten
As with the byte write operation, all inputs are disabled
until completion of the internal write cycle. Refer to
Figure 6 for the address, acknowledge, and data
transfer sequence.
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then no
ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
RETURNED?
NO
YES
NEXT
OPERATION
NO
A WRITE?
YES
ISSUE BYTE
ADDRESS
ISSUE STOP
Refer to Flow 1.
PROCEED
PROCEED
2783 ILL F09
Figure 6. Page Write
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+31
S
T
O
P
SDA LINE
BUS ACTIVITY:
X24645
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
2783 ILL F10.2
6
ICMIC [ IC MICROSYSTEMS ]
