X24C01A
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
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Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
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Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH.
The stop condition is also used by the X24C01A to place
the device into the standby power mode after a
The X24C01A will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been selected,
the X24C01A will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C01A will transmit eight bits of data,
release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24C01A
will continue to transmit data. If an acknowledge is not
detected, the X24C01A will terminate further data trans-
missions. The master must then issue a stop condition to
return the X24C01A to the standby power mode and
read sequence. A stop condition can only be issued after the
transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
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3
ICMIC [ IC MICROSYSTEMS ]
