X24C01
WRITE CYCLE LIMITS
Symbol
t
WR(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
3837 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24C01
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its word address.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
X24C01
ADDRESS
3837 FHD F05
Notes:
(5) Typical values are for T
A
= 25°C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
120
RESISTANCE (KΟ)
100
80
60
40
20
0
0
20
40
R
MIN
V
=
CC MAX
I
OL MIN
t
R
=2.6KΟ
R
MAX
=
C
BUS
MAX.
RESISTANCE
MIN.
RESISTANCE
60
80100120
Allowed
N/A
3837 FHD F15
BUS CAPACITANCE (pF)
10
ICMIC [ IC MICROSYSTEMS ]
