X24C01
Figure 6. ACK Polling Sequence
WRITE OPERATION
COMPLETED
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C01 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the word address
for a
write operation.
If the X24C01 is still busy with the
write operation no ACK will be returned. If the X24C01
has completed the write operation an ACK will be
returned and the controller can then proceed with the
ENTER ACK POLLING
ISSUE
START
next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with exception that the R/W bit of the
word address is set to a one. There are two basic read
operations: byte read and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
ACK
RETURNED?
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
NO
YES
NEXT
OPERATION
NO
clock cycle and then issue a stop condition.
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The X24C01 responds with an acknowledge and
then transmits the eight bits of data. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
A WRITE?
YES
ISSUE STOP
PROCEED
PROCEED
3837 FHD F11
Refer to Figure 7 for the start, word address, read bit,
acknowledge and data transfer sequence.
Figure 7. Byte Read
S
T
BUS ACTIVITY:
MASTER
WORD
A ADDRESS n
R
S
T
O
P
T
S
M
S
SDA LINE
BUS ACTIVITY:
X24C01
P
L
R
A
S
/
C
K
B
B
W
DATA n
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6
ICMIC [ IC MICROSYSTEMS ]
