X24C02
The data output is sequential, with the data from address
and followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing the
entire memory contents to be serially read during
one operation. At the end of the address space (address 255),
the counter “rolls over” to address 0 and the
X24C02 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowl
edge
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C02 continues to output
data for each acknowledge received. The master
terminates this transmission by issuing a stop condition,
omitting the ninth clock cycle acknowledge.
and data transfer sequence.
Figure 9. Sequential Read
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
A
C
A
C
A
C
K
K
K
SDA LINE
BUS ACTIVITY:
X24C02
P
A
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
3838 FHD F15
Figure 10. Typical System Configuration
V
CC
SDA
SCL
MASTER
TRANSMITTER/
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
RECEIVER
RECEIVER
3838 FHD F16
8
ICMIC [ IC MICROSYSTEMS ]
