X24C04
DEVICE OPERATION
The X24C04 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C04 will be considered a slave in all
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All command are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C04 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
applications.
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3839 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3839 FHD F07
3
ICMIC [ IC MICROSYSTEMS ]
