X24C08
WRITE CYCLE LIMITS
Symbol
t
WR(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
3842 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24C08
address.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
X24C08
ADDRESS
3842 FHD F05
Notes:(5)
Typical values are for T
A
= 25°C and nominal supply voltage (5V).
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
OUTPUTS
Will be
steady
Will change
from Low to
120
RESISTANCE (KΟ)
100
80
60
40
20
0
0
20 40
R
MIN
V
=
CC MAX
I
OL MIN
=1.8KΟ
R
MAX
=
t MAX
R
C
BUS
MAX.
RESISTANCE
High
May change
from High to
High
Will change
from High to
Low
MIN.
RESISTANCE
Low
Changing:
State Not
Don’t Care:
Changes
60
80100120
Allowed
N/A
3842 FHD F17
Known
Center Line
is High
BUS CAPACITANCE (pF)
Impedance
11
ICMIC [ IC MICROSYSTEMS ]
