X24C08
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing the
entire memory contents to be serially read during
one operation. At the end of the address space (address
1023) the counter “rolls over” to address 0 and the
X24C08 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowl-
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes; however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C08 continues to out- put
data for each acknowledge received. The read
operation is terminated by the master; by not responding with
an acknowledge and by issuing a stop condition.
edge and data transfer sequence.
Figure 9. Sequential Read
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C08
P
A
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
3842 FHD F15
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
3842 FHD F16
8
ICMIC [ IC MICROSYSTEMS ]
