X25160
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When
CS
is HIGH, the X25160 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25160 will be in the
standby power mode.
CS
LOW enables the X25160,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on
CS
is
required prior to the start of any operation.
Write Protect (WP)
When
WP
is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25160 status register are
disabled, but the part otherwise functions normally.
When
WP
is held HIGH, all functions, including nonvola-
tile writes operate normally.
WP
going LOW while
CS
is
still LOW will interrupt a write to the X25160 status
register. If the internal write cycle has already been
initiated,
WP
going LOW will have no effect on a write.
The
WP
pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install the
X25160 in a system with
WP
pin grounded and still be
able to write to the status register. The
WP
pin functions
will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD
is used in conjunction with the
CS
pin to select the
device. Once the part is selected and a serial sequence
is underway,
HOLD
may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause,
HOLD
must be brought
LOW while SCK is LOW. To resume communication,
HOLD
is brought HIGH, again while SCK is LOW. If the
pause feature is not used,
HOLD
should be held HIGH
at all times.
PIN CONFIGURATION
DIP/SOIC
CS
SO
WP
VSS
1
2
3
4
X25160
8
7
6
5
VCC
HOLD
SCK
SI
TSSOP
CS
SO
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
14
13
12
X25160
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
3064 ILL F02.2
PIN NAMES
SYMBOL
CS
SO
SI
SCK
WP
V
SS
V
CC
HOLD
NC
DESCRIPTION
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3064 PGM T01
2
ICMIC [ IC MICROSYSTEMS ]
