This X25256 device has been acquired by
IC MICROSYSTEMS from Xicor; Inc.
Preliminary Information
256K
X25256
5MHz SPI Serial E
2
PROM with Block Lock
™
32K x 8 Bit
Protection
FEATURES
•5MHz Clock Rate
•Low Power CMOS
—<1µA standby current
—<5mA active current
•2.5V To 5.5V Power Supply
•SPI Modes (0,0 & 1,1)
•32K X 8 Bits
—64 byte page mode
•Block Lock
™
Protection
—Protect first page, first 2 pages, first 4 pages,
first 8 pages, 1/4, 1/2 or all of E
2PROM
array
•Programmable Hardware Write Protection
•Packages —8-
lead XBGA
—8-lead SOIC (JEDEC, EIAJ)
—20-lead TSSOP
DESCRIPTION
2
The X25256 is a CMOS 256K-bit serial E
PROM, inter-
nally organized as 32K x 8. The X25256 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
—In-circuit programmable ROM mode
•Built-In Inadvertent Write Protection
—Power-up/down protection circuitry
—Write enable latch
number of devices to share the same bus.
The X25256 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25256 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire
input to the X25256 disabling all write attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering first page, first 2 pages, 4
—Write protect pin
•Self-Timed Write Cycle
—5ms write cycle time (typical)
•High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
pages, 8 pages, 0, 1/4, 1/2 or all of the memory.
FUNCTIONAL DIAGRAM
Status
Register
Write
Protect
32K Byte
Array
Logic
128
128 X 512
SO
SI
SCK
CS
Command
Decode
HOLD
And
Control
Logic
X-Decode
Protect
128
128 X 512
Logic
248
4
248 X 512
256 X 512
4 X 512
2 X 512
1 X 512
1 X 512
WP
Write
Control
And
Timing
Logic
2
1
1
64
8
Y Decode
Data Register
™
and Block Lock
™
Protection is a trademark of Xicor, Inc.
www.icmic.com
Characteristics subject to change without notice.
1 of 17
ICMIC [ IC MICROSYSTEMS ]
