X76F640
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur- ing a
read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F640 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F640 will be in
standby mode. CS low enables the X76F640, placing it in
the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F640 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
DEVICE OPERATION
There are two primary modes of operation for the
X76F640; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’. The
user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed, can
the data transfer occur.
To ensure the correct communication, RST must remain LOW
under all conditions except when running a
“Response to Reset sequence”.
SOIC
V
SS
CS
SDA
NC
1
2
3
4
8
7
6
5
V
CC
RST
SCL
NC
V
CC
RST
SCL
NC
GND
CS
SDA
NC
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F640 is in a nonvolatile write cycle a “no A
CK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
Vcc
Vss
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
7025 FM T01
PIN CONFIGURATION
Smart Card
7025 FM 02
After each transaction is completed, the X76F640 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
2
ICMIC [ IC MICROSYSTEMS ]
