Philips Semiconductors
Product specification
8-bit synchronous binary down counter
FEATURES
•
Cascadable
•
Synchronous or asynchronous preset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40103 are high-speed Si-gate CMOS
devices and are pin compatible with the “40103” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40103 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40103”
contains a single 8-bit binary counter and has control
inputs for enabling or disabling the clock (CP), for clearing
the counter to its maximum count, and for presetting the
counter either synchronously or asynchronously. All
control inputs and the terminal count output (TC) are
active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT40103
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P
0
to P
7
) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P
0
to P
7
) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P
0
to P
7
) represent
a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
255) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 256 clock pulses long.
The “40103” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
TYPICAL
SYMBOL PARAMETER
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
propagation delay CP to TC
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
30
32
3.5
24
30
31
3.5
27
HCT
ns
MHz
pF
pF
UNIT
1998 Jul 08
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
