AV9173-01
Using the AV9173-01
Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The
AV9173-01
integrates the analog
blocks which make the task much easier.
In the complete video genlock circuit, the primary function of
the
AV9173-01
is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application is
illustrated in Figure 1. The input reference signal for this
circuit is the horizontal synchronization (h-sync) signal. If a
composite video reference source is being used, the h-sync
pulses must be separated from the composite signal. A video
sync separator circuit, such as the National Semiconductor
LM1881, can be used for this purpose.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880 pixel
clocks are desired per h-sync pulse, then the divider ratio is set
to 880. Hence, together the h-sync frequency and external
divider ratio establish the dot clock frequency:
AC specifications (VCO frequency), an input as low as
12kHz (such as NTSC or PAL h-sync) can be used.
The output hook-up of the
AV9173-01
is dictated by the
desired dot clock frequency. The primary consideration is the
internal VCO which operates over a frequency range of
10 MHz to 75 MHz. Because of the selectable VCO output
divider and the additional divider on output CLK2, four
distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
FS0 State
0
0
1
1
Output Used
CLK1
CLK2
CLK1
CLK2
Frequency Range
10 - 75 MHz
5 - 37.5 MHz
2.5 - 18.75 MHz
1.25 - 9.375 MHz
Note that both outputs, CLK1 and CLK2, are available during
operation even though only one is fed back via the external
clock divider.
Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
When unused, inputs FS0 and OE must be tied to either GND
(logic low) or VDD (logic high).
For further discussion of VCO/PLL operation as it applies to
the
AV9173-01,
please refer to the AV9170 application note.
The AV9170 is a similar device with fixed feedback dividers
for skew control applications.
f
OUT
=
f
IN
• N where N is external divide ratio
Both
AV9173-01
input pins IN and FBIN respond only to
negative-going clock edges of the input signal. The h-sync
signal must be constant frequency in the 25 kHz to 1 MHz
range and stable (low clock jitter) for creation of a stable
output clock.
Refer to Application Brief (AB01) for additional details on
use of input frequencies below 25kHz. By following the
guidelines in this brief and meeting the test conditions in the
Figure 1: Typical Application of AV9173-01 in a Video Genlock System
3
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
