IC42S32200
IC42S32200L
T8
T0
T1
T2
T3
T4
T5
T6
T7
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITEA
WRITEB
NOP
NOP
NOP
1 Clk Interval
DIN DIN B
A
DIN B
DIN B
DIN B
3
DQ’s
0
0
1
2
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the
following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be
executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
CAS# latency=2
NOP
WRITEA
READ B
NOP
NOP
NOP
DOUT B
DOUT B
3
DIN A
0
DOUT B
DOUT B
DOUT B
don’t care
don’t care
2
0
1
t
, DQ’s
CK2
CAS# latency=3
DOUT B
DOUT B
DOUT B
3
DIN A
0
don’t care
0
1
2
t
, DQ’s
CK3
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
DIN
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/
tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
COMMAND
WRITE
Precharge
NOP
NOP
Activate
ROW
NOP
NOP
n+1
BANK
COL n
(S)
BANK
ADDRESS
DQ
t
WR
DIN
n
: don t care
Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
12
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
