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ICS1893BKILF 参数 Datasheet PDF下载

ICS1893BKILF图片预览
型号: ICS1893BKILF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用: 电信集成电路
文件页数/大小: 133 页 / 1984 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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Integrated Circuit Systems, Inc.
ICS1893BF
General
The ICS1893BF is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.
The ICS1893BF is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1893BF incorporates Digital-Signal Processing (DSP)
control in its Physical-Medium Dependent (PMD) sub layer. As
a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100MHz. With this ICS-patented
technology, the ICS1893BF can virtually eliminate errors from
killer packets.
The ICS1893BF provides a Serial-Management Interface for
exchanging command and status information with a
Sta t i o n - M a n a g e m e n t ( S TA ) e n t i t y. T h e I C S 1 8 9 3 B F
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of 10
Mb/s or 100Mb/s.
The ICS1893BF is available in a 300-mil 48-lead SSOP
pac k a g e . T h e I CS 1 89 3 B F s h a r e s t h e s a m e p r o v en
performance circuitry with the ICS1893AF but is not a
pin-for-pin replacement of the 1893AF. An application note for
a dual footprint layout to accommodate ICS1893AF or
ICS1893BF is available on the ICS website.
Document Type:
Data Sheet
Document Stage: Rev. C Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
Features
Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
Single-chip, fully integrated PHY provides PCS, PMA, PMD,
and AUTONEG sub layers functions of IEEE standard.
10Base-T and 100Base-TX IEEE 8802.3 compliant
Single 3.3V power supply
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
– Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 400 mW)
Power-Down mode typically 21mW
Clock and crystal supported
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Small footprint 48-pin 300 mil. SSOP package
Also available in small footprint 56-pin 8x8 MLF2 package
Available in Industrial Temp and Lead Free
Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines,
printers.
ICS1893BF Block Diagram
100Base-T
10/100 MII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
ICS1893BF, Rev. C, 9/29/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
September, 2005