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ICS300M 参数 Datasheet PDF下载

ICS300M图片预览
型号: ICS300M
PDF下载: 下载PDF文件 查看货源
内容描述: QTClock ™快速打开时钟合成器 [QTClock⑩ Quick Turn Clock Synthesizer]
分类和应用: 时钟
文件页数/大小: 4 页 / 68 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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ICS300/ICS301/ICS302
QTClock™ Quick Turn Clock Synthesizer
Description
The ICS300 and ICS301 QTClocks™ generate a
high quality, high frequency clock output and a
reference from a low frequency crystal or clock
input. They are designed to replace crystals and
crystal oscillators in most electronic systems. The
ICS302 can accept a higher frequency clock input
to generate up to 200 MHz. The devices contain a
One Time Programmable (OTP) ROM which is
factory programmed with the PLL divider values
to output a broad range of frequencies, from 6 to
200 MHz, allowing customer requests for different
frequencies to be shipped in 1-3 days. Using
Phase-Locked-Loop (PLL) techniques, the devices
run from a standard fundamental mode,
inexpensive crystal, or clock. They are smaller and
less expensive than one oscillator.
Features
• Packaged as 8 pin SOIC
• Quick turn frequency programming allows
samples in one to three days
• Replaces nearly any crystal or oscillator
• ICS300 produces up to 100 MHz at 3.3V,
ICS301 produces up to 200 MHz at 3.3V
ICS302 accepts up to 125 MHz clock input
• Easy to cascade with ICS5xx series
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 125 MHz
• Low jitter - 50 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55
• Operating voltages of 3.0 to 5.5V
• Full CMOS level outputs with 25mA drive
capability at TTL levels
• Tri-state output + PLL power down pin
• Advanced, low power CMOS process
Block Diagram
VDD GND
Crystal
or clock
input
OTP
ROM
with PLL
Divider
Values
X1/ICLK
PLL
Clock
Synthesis
and Control
Circuitry
Output
Buffer
CLK
Crystal
Oscillator
X2
Divide
Logic and
Output
Buffer
REF
PDTS (both outputs and PLL)
MDS 300QT E
1
Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com