ICS525-01/02/11/12
User Configurable Clock
Parameter
Short Circuit Current
Input Capacitance
On-chip Pull-up Resistor
Symbol
C
IN
R
PU
Conditions
CLK and REF outputs
V, R, S pins and pin 19
V, R, S pins and pin 19
Min.
Typ.
±55
4
270
Max.
Units
mA
pF
kΩ
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V
Parameter
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
Output Clock Duty Cycle, OD =
1 (-02 and -12 only)
Power-down Time, PD low to
clocks stopped
Power-up Time, PD high to
clocks stable
Absolute Clock Period Jitter,
ICS525-01, Note 2
One Sigma Clock Period Jitter,
ICS525-01, Note 2
Absolute Clock Period Jitter,
ICS525-02, Note 2
One Sigma Clock Period Jitter,
ICS525-02, Note 2
Absolute Clock Period Jitter,
ICS525-11, Note 2
One Sigma Clock Period Jitter,
ICS525-11, Note 2
Absolute Clock Period Jitter,
ICS525-12, Note 2
One Sigma Clock Period Jitter,
ICS525-12, Note 2
Symbol
F
IN
Conditions
Crystal input
Clock input
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
At VDD/2
At VDD/2
Min.
5
2
Typ.
Max.
27
50
Units
MHz
MHz
ns
ns
1
1
45
40
35
49 to
51
55
60
65
50
10
%
%
ns
ms
ps
ps
ps
ps
ps
ps
ps
ps
t
ja
t
js
t
ja
t
js
t
ja
t
js
t
ja
t
js
Deviation from mean
One Sigma
Deviation from mean
One Sigma
Deviation from mean
One Sigma
Deviation from mean
One Sigma
±140
45
±85
30
±160
40
±160
40
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
7
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
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