ICS527-02
Clock Slicer User Configurable PECL Input Zero Delay Buffer
Description
The ICS527-02 Clock Slicer is the most flexible way to
generate a CMOS output clock from a PECL input
clock with zero skew. The user can easily configure the
device to produce nearly any output clock that is
multiplied or divided from the input clock. The part
supports non-integer multiplications and divisions. A
SYNC pulse indicates when the rising clock edges are
aligned with zero skew. Using Phase-Locked Loop
(PLL) techniques, the device accepts an input clock up
to 200 MHz and produces an output clock up to 160
MHz.
The ICS527-02 aligns rising edges on PECLIN with
FBIN at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
For a CMOS input and PECL output with zero delay,
use the ICS527-03.
Features
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Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
PECL IN to CMOS OUT
Pin selectable dividers
Zero input to output skew
User determines the output frequency—no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz to 200 MHz
Output clock frequencies from 2.5 MHz to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Industrial temperature version available
Block Diagram
R6:R0
7
PECLIN
PECLIN
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
FBIN
Feedback
Divider
2
VCO
Output
Divider
Divide
by 2
1
0
33 ohm
CLK2
Feedback can
come from
CLK1 or CLK2
(not both)
2
VDD
33 ohm
CLK1
SYNC
7
F6:F0
GND
PDTS
2
S1:S0
DIV2
MDS 527-02 F
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 022806
tel (408) 297-1201
●
www.icst.com
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