ICS527-01
Clock Slicer™
User Configurable Zero Delay Buffer
Description
The ICS527-01 Clock Slicer™ is the most flexible
way to generate an output clock from an input
clock with zero skew. The user can easily configure
the device to produce nearly any output clock that
is multiplied or divided from the input clock. The
part supports non-integer multiplications and
divisions. A SYNC pulse indicates the rising clock
edges that are aligned with zero skew. Using
Phase-Locked Loop (PLL) techniques, the device
accepts an input clock up to 200 MHz and
produces an output clock up to 160 MHz.
The ICS527-01 aligns rising edges on ICLK and
FBIN at a ratio determined by the reference and
feedback dividers.
For configurable clocks that do not require
zero delay, use the ICS525.
Features
• Packaged as 28 pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• User determines the output frequency - no
software needed
• Slices frequency or period
• SYNC pulse output indicates aligned edges
• Input clock frequency of 600 kHz - 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55 up to 160 MHz
• Operating voltage of 3.3 V (±10%)
• Pin selectable double drive strength
• Multiple outputs available when combined with
Buffalo clock drivers
• Zero input to output skew
• Industrial temperature version available
• Advanced, low power CMOS process
S1:S0
2
PDTS
CLK1
PLL
PDTS
÷2
SYNC
1
0
Block Diagram
R6:R0
7
ICLK
Reference
Divide
Feedback
Divide
7
2XDRIVE
FBIN
CLK2
DIV2
PDTS
OECLK2
F6:F0
External feedback from CLK1 or CLK2 (not both).
1
Revision 020801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com
MDS 527-01 B
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
