ICS5342
GENDAC
16-Bit Integrated Clock-LUT-DAC
General Description
The ICS5342 GENDAC is a combination of dual programma-
ble clock generators, a 256 x 18-bit RAM, and a triple 8-bit
video DAC. The GENDAC supports 8-bit pseudo color appli-
cations, as well as 15-bit, 16-bit, and 24-bit True Color bypass
for high speed, direct access to the DACs.
The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators use
Phase Locked Loop (PLL) technology to provide program-
mable frequencies for use in the graphics subsystem. The vid-
eo clock contains 8 frequencies, all of which are
programmable by the user. The memory clock has two pro-
grammable frequency locations.
The three 8-bit DACs on the ICS5342 are capable of driving
singly or doubly-terminated 75
Ω
loads to nominal 0 - 0.7
volts at pixel rates up to 135 MHz. Differential and integral
linearity errors are less than 1 LSB over full temperature and
VDD ranges. Monotonicity is guaranteed by design. On-chip
pixel mask register allows displayed colors to be changed in
a single write cycle rather than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock) gen-
eration for graphics, using patented techniques to produce
low jitter video timing.
Features
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Triple video DAC, dual clock generator, and 16 bit pixel
port
Dynamic mode switch allows switching of color depth
on a pixel by pixel basis
24 (packed and sparse), 16, 15, or 8-bit pseudo color
pixel mode supports True Color, Hi-Color, and VGA
modes
High speed 256 x 6 x 3 color palette (135 MHz) with
bypass mode and 8-bit DACs
Eight programmable video (pixel) clock frequencies
(CLK0)
DAC power down in blanking mode
Anti-sparkle circuitry
On-chip loop filters reduce external components
Standard CPU interface
Single external crystal (typically 14.318 MHz)
Monitor sense
Internal voltage reference
135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions
Very low clock jitter
Two latched frequency select pins or three non-latched
frequency select pins (programmable)
Hardware video checksum for manufacturing tests
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Block Schematic
PCLK
COMPARE
24
P0-P15
BUFF.
LATCH
PIXEL
ADR
AND
MASK
D0-D7
WR*
RD*
RS0-RS2
STROBE
CS0-CS2
BLANK*
16
MICRO-
PROCESSOR
INTERFACE
8
16
TIMING
GEN.
CTL
8 PLL
PARAMETER &
CLK0 PLL
BYPS
SENSE*
RED
GREEN
BLUE
RSET
VREF
COLOR
PALETTE
256 x 18
BIT
MUX
18
NORM
LATCH
24
TRIPLE
6/8-BIT
DAC
MUX.
PCLK
2X
MODE
CLK0
XIN
XTAL
OSC
XOUT
1 PLL
PARAMETER &
CLK1 PLL
CLK1
5342_01.ai
REV. 0.9.0
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