ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise,
VDD=3.3 V ±10%,
Ambient Temperature -40 to +85°C
Parameter
Input Frequency
Output Frequency
Output High Voltage
1,2
Output Low Voltage
Crossing Point
Voltage
1,2
Crossing Point
Voltage
1,2,4
Jitter, Cycle-to-Cycle
1,3
Modulation Frequency
Rise Time
1,2
Fall Time
1,2
Rise/Fall Time
Variation
1,2
Skew between outputs
Duty Cycle
1,3
Output Enable Time
5
Output Disable Time
5
Stabilization Time
Spread Change Time
t
STABLE
t
OR
t
OF
1,2
Symbol
Conditions
Min.
25
Typ.
25
Max.
200
Units
MHz
MHz
mV
mV
mV
mV
ps
V
OH
V
OL
Notes 1, 2
Notes 1, 2
Absolute, Notes 1, 2
Variation over all edges, Notes 1, 2, 4
Notes 1, 3
Spread spectrum
From 0.175 V to 0.525 V, Notes 1, 2
From 0.525 V to 0.175 V, Notes 1, 2
Notes 1, 2
At VDD/2
Notes 1, 3
All outputs, Note 5
All outputs, Note 5
From power-up VDD=3.3 V
660
-150
250
700
0
350
850
550
140
60
30
175
175
31.5
332
344
33
700
700
125
50
45
10
10
3.0
3.0
55
kHz
ps
ps
ps
ps
%
us
us
ms
ms
t
SPREAD
Settling period after spread change
Note 1: Test setup is R
L
=50 ohms with 2 pF, Rr = 475Ω (1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
MDS 557-03 E
In te grated Circuit Systems
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