ICS558-02
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
Description
The ICS558-02 accepts a high-speed LVHSTL input
and provides four CMOS low skew outputs from a
selectable internal divider (divide by 3, divide by 4). The
four outputs are split into two banks of two outputs.
Each bank has a separate output enable to tri-state the
output buffers.
The ICS558-02 is a member of the ICS Clock Blocks
TM
family of clock generation, synchronization, and
distribution devices.
Features
•
•
•
•
•
•
16-pin TSSOP package
LVHSTL inputs
Accepts up to 250 MHz input frequency
Four low skew (<250 ps) outputs
Selectable internal divider of 3 or 4
Operating voltage of 3.3 V
Block Diagram
VDD
4
OE0
CLK1
CLK2
Output Divide
/3 or /4
CLK3
CLK4
HCLK
HCLK
SEL
3
GND
OE1
MDS 558-02 D
I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 020504
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
